roadkill Posted October 6, 2008 Share Posted October 6, 2008 The OMAP3 has a pretty bog-standard Cortex A-8. It has a slightly slower floating point unit, but if you want to it can do up to 2 sp floating point ops per clock, but that's only if you use it in NEON mode (think SSE), otherwise it's not as fast at doing floating point.So, if you tune it, you can do quite well. If you don't tune it, it is not as good as it could be. The problem is only TI can do the tuning for that since the NEON thing is very closed, even though it seems to be extremely capable as in their HD decoding demos. It's also only really suitable for processing large batches of floats at a time, which whilst in an ideal world is what is done already to use vector instructions it is far from the reality of what compilers tend to spit out. It is similar to how the DC does things, which conceivably might help, but the DC does four per cycle (iirc) at about half the clock rate, so you're dangerously close to not being able to absorb the inevitable emulation overhead. Writing an SH4 -> ARM + NEON code translator strikes me as a niche activity. The good thing is that the ARM does have the whole shift per instruction thing, meaning you can do fixed point in a much more optimal way than on most other instruction sets, which is how the DS does things. Link to comment Share on other sites More sharing options...
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